ML4039D

The ML4039D is a fully featured 200G BERT that can be configured as a 4-channel PAM4 30 GBaud or 4-channel NRZ 30 Gbps lanes. The receivers support FEC decoding (802.3bj KR4/scaled KP4) and will return the frame loss ratio for FEC scenarios and BER for unframed data. The receivers also show the eye’s Histogram and the channel’s SNR over time. The transmitters Support all standard test patterns mandated by IEEE and OIF such as PRBSQ13, SSPRQ, PRBSQ31, QPRBS13-CEI, etc… The user may also program...

BERT and DSO

-Jitter Analysis -Eye Measurements -Eye Mask Test -Advanced Pattern Acquisition -Pre-emphasis Measurement -Automated J2/J9 measurements -Scope with integrated CDR -Jitter Components Decomposition -NRZ & PAM4 Eye Mask Test -S21 Measurements -Clock Recovery Option ...

ML4086

The ML4086 is designed as a CFP2 to QSFP28 interconnect adapter  housed in a CFP2 form factor, including a MSA compliant hardware and management interface implementation making it compatible with standard CFP2 Host ports . At the QSFP28 side, the adapter will provide a standard QSFP28 Host connector: implementing a SFF compliant driver which will be capable of operating standard QSFP28 transceivers. ...

ML4046

ML4046 is used for testing uQSFP transceiver ports under board level tests. Substituting a full-featured uQSFP transceiver with the ML4046 provides a cost effective low loss method for uQSFP port testing via electrical loopback. It can emulate power classes from 1 to 7 (loading +3.3V voltage supply). ...

ML4024

SFP28 Host (Small Form Factor 28) MSA Compliant Master Host board ML4024 provides an efficient and easy method for programming and testing 28G SFP28 transceivers.  The ML4024 includes a complete Window’s based software and user manual to enable intuitive memory map programming and testing, controlled via mini B USB.  The SFP28 Host is designed to simulate an ideal environment for SFP28 transceivers’ module and cable testing, characterization and manufacturing tests. Its properties make the...

ML407

The ML407 is an add-on clock synthesizer for the ML4039 BERT(Bit Error Ratio Tester) series that is intended for multi-UI sinusoidal jitter generation. It generates the necessary SJ required for doing electrical stressed input compliance testing for 100Gbps modules and hosts as per OIF-CEI VSR28 and IEEE802.3 (CAUI-4).   ...

ML4004-PAM

The ML4004-PAM is a state of the art dual Channel PAM4 BERT and Digital Sampling Oscilloscope that is integrated in an ultra-compact form factor. USB/Ethernet controlled, it performs accurate eye-diagram analysis to characterize the quality of transmitters and receivers. ...